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SY10E141

SY100E141

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

s 700MHz min. shift frequency

s 8 bits wide

s Bi-directional

s Four selectable modes for full functionality

s Asynchronous Master Reset

s Fully compatible with industry standard 10KH,

100K ECL levels

s Internal 75K

s Fully compatible with Motorola MC10E/100E141

s Pin-compatible with E241

s Available in 28-pin PLCC package

FEATURES

The SY10/100E141 are 8-bit, full-function shift registers

designed for use in new, high-performance ECL systems.

The E141 performs serial/parallel in and serial/parallel out,

parallel input data, while DL/DR accept serial input data for

left/right shifting.

of operation: Load, Hold, Shift Left and Shift Right, as

shown in the Truth Table. Input data is clocked into the

register on the rising clock edge after meeting the minimum

set-up time. A logic HIGH on the Master Reset (MR) pin

asynchronously resets all the registers to zero.

DESCRIPTION

BLOCK DIAGRAM

DQ

R

D

Q

D

Q

R

DQ

R

DL

DR

BITS 1-6

SEL1

SEL0

CLK

MR

SY10E141

SY100E141

8-BIT SHIFT

REGISTER

Rev.: E

Amendment: /0

Issue Date:

March 2006

Pin

Function

Parallel Data Inputs

DL, DR

Serial Data Inputs

Mode Select Inputs

CLK

Clock

Data Outputs

MR

Master Reset

PIN NAMES