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AT45DB011D Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT45DB011D Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 52 page  4 3639B–DFLASH–02/07 AT45DB011D [Preliminary] 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB011D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis. The erase operations can be performed at the chip, sector, block or page level. Figure 4-1. Memory Architecture Diagram 5. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 15-1 through 15-7. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first. Buffer addressing for the DataFlash standard page size (264 bytes) is referenced in the datasheet using the terminology BFA8 - BFA0 to denote the 9 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA8 - PA0 and BA8 - BA0, where PA8 - PA0 denotes the 9 address bits required to designate a page address and BA8 - BA0 denotes the 9 address bits required to designate a byte address within the page. For the “Power of 2” binary page size (256 bytes), the Buffer addressing is referenced in the datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology A16 - A0, where A16 - A8 denotes the 9 address bits required to desig- nate a page address and A7 - A0 denotes the 8 address bits required to designate a byte address within a page. SECTOR 0a = 8 Pages 2,048/2,112 bytes SECTOR 0b = 120 Pages 31,744/32,726 bytes Block = 2,048/2,112 bytes 8 Pages SECTOR 0a Page = 256/264 bytes PAGE 0 PAGE 1 PAGE 6 PAGE 7 PAGE 8 PAGE 9 PAGE 510 PAGE 511 PAGE 14 PAGE 15 PAGE 16 PAGE 17 PAGE 18 SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE BLOCK 0 BLOCK 1 BLOCK 13 BLOCK 14 BLOCK 15 BLOCK 16 BLOCK 62 BLOCK 63 BLOCK 28 BLOCK 29 BLOCK 30 BLOCK 31 SECTOR 3 = 128 Pages 32,768/33,792 bytes BLOCK 2 SECTOR 1 = 128 Pages 32,768/33,792 bytes SECTOR 2 = 128 Pages 32,768/33,792 bytes |
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