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AT45DB321D Datasheet(PDF) 23 Page - ATMEL Corporation |
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AT45DB321D Datasheet(HTML) 23 Page - ATMEL Corporation |
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23 / 55 page  23 3597H–DFLASH–02/07 AT45DB321D [Preliminary] 11.4 Status Register Read The status register can be used to determine the device’s ready/busy status, page size, a Main Memory Page to Buffer Compare operation result, the Sector Protection status or the device density. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the status register, the CS pin must be asserted and the opcode of D7H must be loaded into the device. After the opcode is clocked in, the 1-byte status register will be clocked out on the output pin (SO), starting with the next clock cycle. The data in the status register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next eight clock cycles. After the one byte of the status register has been clocked out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled). The data in the status register is constantly updated, so each repeating sequence will output new data. Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. Since the data in the status register is constantly updated, the user must toggle SCK pin to check the ready/busy status. There are several operations that can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program, Main Memory Page Program through Buffer, Page Erase, Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. Bit 1 in the Status Register is used to provide information to the user whether or not the sector protection has been enabled or disabled, either by software-controlled method or hardware-con- trolled method. A logic 1 indicates that sector protection has been enabled and logic 0 indicates that sector protection has been disabled. Bit 0 in the Status Register indicates whether the page size of the main memory array is config- ured for “power of 2” binary page size (512 bytes) or DataFlash standard page size (528 bytes). If bit 0 is a 1, then the page size is set to 512 bytes. If bit 0 is a 0, then the page size is set to 528 bytes. The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the AT45DB321D, the four bits are 1101 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices. The device density is not the same as the density code indicated in the JEDEC device ID information. The device density is provided only for backward compatibility. Table 11-1. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDY/BUSY COMP 1 1 0 1 PROTECT PAGE SIZE |
Similar Part No. - AT45DB321D_07 |
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Similar Description - AT45DB321D_07 |
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