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AT45DB642D-TU Datasheet(PDF) 39 Page - ATMEL Corporation |
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AT45DB642D-TU Datasheet(HTML) 39 Page - ATMEL Corporation |
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39 / 55 page  39 3542F–DFLASH–09/06 AT45DB642D 21.8 Utilizing the Rapid8™ Function The Rapid8 functions like RapidS but with 8 bits of data instead of 1 bit. A full clock cycle must be used to transmit data back and forth across the 8 bit bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK. For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the fall- ing edge of SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of SCK. Figure 21-2. Rapid8 Mode 21.9 Reset Timing Note: The CS signal should be in the high state before the RESET signal is deasserted. SCK I/O 7-0 1 234567 8 9 101112131415 MOSI = Master Out, Slave In MISO = Master In, Slave Out The Master would be the ASIC/MCU and the Slave would be the memory device. The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK. The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK. A. Master clocks out BYTE 1 on the rising edge of SCK. B. Slave clocks in BYTE 1 on the next rising edge of SCK. C. Master clocks out BYTE 2 on the same rising edge of SCK. D. Slave clocks in BYTE 6 (last input byte). E. Slave clocks out BYTE a (first output byte). F. Master clocks in BYTE a. G. Master clocks in BYTE h (last output byte). A B C D E F G Slave CS BYTE 6 BYTE 5 BYTE 4 BYTE 3 BYTE 2 BYTE 1 BYTE a BYTE b BYTE c BYTE d BYTE e BYTE f BYTE g BYTE h t V CS SCK/CLK RESET SO or I/O7 - I/O0 (OUTPUT) HIGH IMPEDANCE HIGH IMPEDANCE SI or I/O7 - I/O0 (INPUT) tRST tREC tCSS |
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