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AT45DB642D-TU Datasheet(PDF) 36 Page - ATMEL Corporation |
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AT45DB642D-TU Datasheet(HTML) 36 Page - ATMEL Corporation |
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36 / 55 page  36 3542F–DFLASH–09/06 AT45DB642D 21. AC Waveforms Six different timing waveforms are shown below. Waveform 1 shows the SCK/CLK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK/CLK signal being high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK/CLK signal is still low (SCK/CLK low time is specified as t WL). Timing waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 66 MHz. Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively. Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and waveform 2, except that output SO is not restricted to become valid during the t WL period. These timing waveforms are valid over the full frequency range (max- imum frequency = 66 MHz) of the RapidS serial case. Waveform 5 and waveform 6 are for 8-bit Rapid8 interface over the full frequency range of operation (maximum frequency = 50 MHz). 21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66 MHz) 21.2 Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66 MHz) Note: To operate the device at 50 MHz in SPI mode, the combined CPU setup time and rise/fall time should be less than 2 ns. CS SCK/CLK SI SO tCSS VALID IN tH tSU tWH tWL tCSH tCS tV HIGH IMPEDANCE VALID OUT tHO tDIS HIGH IMPEDANCE CS SCK/CLK SO tCSS VALID IN tH tSU tWL tWH tCSH tCS tV HIGH Z VALID OUT tHO tDIS HIGH IMPEDANCE SI |
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