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AT45DB642D-TU Datasheet(PDF) 35 Page - ATMEL Corporation |
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AT45DB642D-TU Datasheet(HTML) 35 Page - ATMEL Corporation |
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35 / 55 page  35 3542F–DFLASH–09/06 AT45DB642D Note: Values are based on device characterization, not 100% tested in production. 19. Input Test Waveforms and Measurement Levels tR, tF < 2 ns (10% to 90%) 20. Output Test Load Table 18-5. AC Characteristics – Rapid8 8-bit Interface Symbol Parameter Min Typ Max Units f SCK1 CLK Frequency 50 MHz f CAR1 CLK Frequency for Continuous Array Read 50 MHz t WH CLK High Time 9 ns t WL CLK Low Time 9 ns t CS Minimum CS High Time 50 ns t CSS CS Setup Time 5 ns t CSH CS Hold Time 5 ns t CSB CS High to RDY/BUSY Low 100 ns t SU Data In Setup Time 2 ns t H Data In Hold Time 5 ns t HO Output Hold Time 0 ns t DIS Output Disable Time 12 ns t V Output Valid 12 ns t WPE WP Low to Protection Enabled 1µs t WPD WP High to Protection Disabled 1µs t EDPD CS High to Deep Power-down Mode 3 µs t RDPD CS High to Standby Mode 30 µs t XFR Page to Buffer Transfer Time 400 µs t comp Page to Buffer Compare Time 400 µs t EP Page Erase and Programming Time (1,024/1,056 bytes) 17 40 ms t P Page Programming Time (1,024/1,056 bytes) 3 6 ms t PE Page Erase Time (1,024/1,056 bytes) 15 35 ms t BE Block Erase Time (8,192/8,448 bytes) 45 100 ms t SE Sector Erase Time (262,144/270,336 bytes) 1.6 5 s t RST RESET Pulse Width 10 µs t REC RESET Recovery Time 1µs AC DRIVING LEVELS AC MEASUREMENT LEVEL 0.45V 1.5V 2.4V DEVICE UNDER TEST 30 pF |
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