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AT45DB642D-TU Datasheet(PDF) 34 Page - ATMEL Corporation |
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AT45DB642D-TU Datasheet(HTML) 34 Page - ATMEL Corporation |
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34 / 55 page  34 3542F–DFLASH–09/06 AT45DB642D Note: 1. Values are based on device characterization, not 100% tested in production. Table 18-4. AC Characteristics – RapidS/Serial Interface Symbol Parameter Min Typ Max Units fSCK SCK Frequency 66 MHz f CAR1 SCK Frequency for Continuous Array Read 66 MHz f CAR2 SCK Frequency for Continuous Array Read (Low Frequency) 33 MHz t WH SCK High Time 6.8 ns tWL SCK Low Time 6.8 ns tSCKR (1) SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns t SCKF (1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tCS Minimum CS High Time 50 ns tCSS CS Setup Time 5 ns t CSH CS Hold Time 5 ns tCSB CS High to RDY/BUSY Low 100 ns tSU Data In Setup Time 2 ns t H Data In Hold Time 3 ns tHO Output Hold Time 0 ns tDIS Output Disable Time 6ns t V Output Valid 6ns tWPE WP Low to Protection Enabled 1 µs t WPD WP High to Protection Disabled 1 µs t EDPD CS High to Deep Power-down Mode 3 µs tRDPD CS High to Standby Mode 30 µs t XFR Page to Buffer Transfer Time 400 µs t comp Page to Buffer Compare Time 400 µs tEP Page Erase and Programming Time (1,024/1,056 bytes) 17 40 ms t P Page Programming Time (1,024/1,056 bytes) 3 6 ms t PE Page Erase Time (1,024/1,056 bytes) 15 35 ms tBE Block Erase Time (8,192/8,448 bytes) 45 100 ms t SE Sector Erase Time (262,144/270,336 bytes) 1.6 5 s t CE Chip Erase Time TBD TBD s tRST RESET Pulse Width 10 µs t REC RESET Recovery Time 1 µs |
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