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AT45DB642D-TU Datasheet(PDF) 21 Page - ATMEL Corporation |
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AT45DB642D-TU Datasheet(HTML) 21 Page - ATMEL Corporation |
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21 / 55 page  21 3542F–DFLASH–09/06 AT45DB642D Figure 10-3. Program Security Register 10.2.2 Reading the Security Register The Security Register can be read by first asserting the CS pin and then clocking in an opcode of 77H followed by three dummy bytes if using the serial interface and seven dummy bytes if using the 8-bit interface. After the last don't care bit has been clocked in, the content of the Security Register can be clocked out on the SO or I/O7 - I/O0 pins. After the last byte of the Security Register has been read, additional pulses on the SCK/CLK pin will simply result in undefined data being output on the SO or I/O7 - I/O0 pins. Deasserting the CS pin will terminate the Read Security Register operation and put the SO or I/O7 - I/O0 pins into a high-impedance state. Figure 10-4. Read Security Register Data Byte n Opcode Byte 1 Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 Data Byte n + 1 Data Byte n + x CS Each transition represents 8 bits SI or IO 7 - IO0 Opcode X X X Data Byte n Data Byte n + 1 CS Data Byte n + x Each transition represents 8 bits SI or IO 7 - IO0 SO or IO 7 - IO0 |
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