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AT45DB642D-TU Datasheet(PDF) 17 Page - ATMEL Corporation |
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AT45DB642D-TU Datasheet(HTML) 17 Page - ATMEL Corporation |
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17 / 55 page  17 3542F–DFLASH–09/06 AT45DB642D The Program Sector Protection Register command utilizes the internal SRAM buffer for process- ing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued. Figure 9-3. Program Sector Protection Register 9.1.3 Read Sector Protection Register Command To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 32H and a series of dummy bytes (3 dummy bytes if using the serial interface or 7 dummy bytes if using the 8-bit interface) must be clocked in via the SI or I/O7 or I/O0 pins. After the last bit of the opcode and dummy bytes have been clocked in, any addi- tional clock pulses on the SCK/CLK pins will result in data for the content of the Sector Protection Register being output on the SO or I/O7-I/O0 pins. The first byte corresponds to sec- tor 0 (0a, 0b), the second byte corresponds to sector 1 and the last byte (byte 32) corresponds to sector 31. Once the last byte of the Sector Protection Register has been clocked out, any addi- tional clock pulses will result in undefined data being output on the SO or I/O pins. The CS must be deasserted to terminate the Read Sector Protection Register operation and put the output into a high-impedance state. Note: xx = Dummy Byte Serial Interface = 3 Dummy Bytes 8-bit Interface = 7 Dummy Bytes Figure 9-4. Read Sector Protection Register Command Byte 1 Byte 2 Byte 3 Byte 4 Program Sector Protection Register 3DH 2AH 7FH FCH Data Byte n Opcode Byte 1 Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 Data Byte n + 1 Data Byte n + 31 CS Each transition represents 8 bits SI or IO 7 - IO0 Command Byte 1 Byte 2 Byte 3 Byte 4 Read Sector Protection Register 32H xxH xxH xxH Opcode X X X Data Byte n Data Byte n + 1 CS Data Byte n + 31 SI or IO 7 - IO0 SO or IO 7 - IO0 Each transition represents 8 bits |
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