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AT45DB321C Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT45DB321C Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 40 page  7 3387L–DFLASH–6/06 AT45DB321C 5.2.6 Main Memory Page Program Through Buffer This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI) and then programmed into a specified page in the main memory. To initiate the operation, an 8-bit opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three address bytes. The address bytes are comprised of one reserved bit, 13 page address bits (PA12-PA0) that select the page in the main memory where data is to be written, and 10 buffer address bits (BFA9-BFA0) that select the first byte in the buffer to be written. After all address bytes are clocked in, the part will take data from the input pins and store it in the speci- fied data buffer. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t EP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. 5.3 Additional Commands 5.3.1 Main Memory Page to Buffer Transfer A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes comprised of one reserved bit, 13 page address bits (PA12- PA0), which specify the page in main memory that is to be transferred, and 10 don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (t XFR), the status register can be read to determine whether the transfer has been com- pleted or not. Table 5-1. Block Erase Addressing PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block 00 00 000 00 0 X X X 0 00 00 000 00 1 X X X 1 00 00 000 01 0 X X X 2 00 00 000 01 1 X X X 3 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 11 11 111 10 0 X X X 1020 11 11 111 10 1 X X X 1021 11 11 111 11 0 X X X 1022 11 11 111 11 1 X X X 1023 |
Similar Part No. - AT45DB321C_06 |
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Similar Description - AT45DB321C_06 |
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