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NCP5425DBR2G Datasheet(PDF) 20 Page - ON Semiconductor |
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NCP5425DBR2G Datasheet(HTML) 20 Page - ON Semiconductor |
20 / 22 page ![]() NCP5425 http://onsemi.com 20 Grounding the Mode pin enables an internal clamp to limit the Comp 2 voltage excursions during overcurrent faults. Without this clamp, the output voltage (Vout1 and Vout2) can overshoot the regulated output voltages when the fault is removed. For a single output two−phase application the Mode pin must be floating, which disables the clamp and permits a larger current−sharing reference voltage range. The Comp1 pin is always clamped, because it is regulated to a fixed internal voltage (0.8 V). The simplest way to provide a Controller 2 reference is by using the Controller 1 feedback voltage. This will provide a 0.8 V reference for regulation, and also causes the Controller 2 output to track the Controller 1 output during transients. With a voltage reference established and the Mode pin floating, Controller 2 can function as an independent Buck regulator. Vin Q1 L1 R1 R2 + − Vfb1 Q2 Master Error Amp Internal 0.8 V Ref. L2 + − Vfb2 Vref2 Slave Error Amp Q3 Q4 Figure 15. Dual Output Configuration C1 R3 C2 Vref1 R4 Vout1 Vout2 Adding External Slope Compensation Today’s voltage regulators are expected to meet very stringent load transient requirements. One of the key factors in achieving tight dynamic voltage regulation is low ESR. Low ESR at the regulator output results in low output voltage ripple. The consequence is, however, that very little voltage ramp exists at the control IC feedback pin (VFB), resulting in increased regulator sensitivity to noise and the potential for loop instability. In applications where the internal slope compensation is insufficient, the performance of the NCP5425−based regulator can be improved through the addition of a fixed amount of external slope compensation at the output of the PWM Error Amplifier (the COMP pin) during the regulator off−time. Referring to Figure 8, the amount of voltage ramp at the COMP pin is dependent on the gate voltage of the lower (synchronous) FET and the value of resistor divider formed by R1and R2. VSLOPECOMP + VGATE(L) R2 R1 ) R2 (1−e −1 t ) where: VSLOPECOMP = amount of slope added; VGATE(L) = lower MOSFET gate voltage; R1, R2 = voltage divider resistors; t = tON or tOFF (switch off−time); t = RC constant determined by C1 and the parallel combination of R1, R2 neglecting the low driver output impedance. Figure 16. RC Filter Provides the Proper Voltage Ramp at the Beginning of each On−Time Cycle COMP NCP5425 GATE(L) R2 C1 R1 To Synchronous FET The artificial voltage ramp created by the slope compensation scheme results in improved control loop stability provided that the RC filter time constant is smaller than the off−time cycle duration (time during which the lower MOSFET is conducting). It is important that the series combination of R1 and R2 is high enough in resistance to avoid loading the GATE(L) pin. Also, C1 should be very small (less than a few nF) to avoid heating the part. |
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