NCP5425DBR2G datasheet(16/22 Pages) ONSEMI

Part #	NCP5425DBR2G

Description	Dual Synchronous Buck Controller

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Manufacturer	ONSEMI [ON Semiconductor]

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NCP5425

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16

where:

IRMS(H) = maximum switching MOSFET RMS current;

IL(PEAK) = inductor peak current;

IL(VALLEY) = inductor valley current;

D = duty cycle.

Once the RMS current through the switch is known, the

switching MOSFET conduction losses can be calculated by:

PRMS(H) + IRMS(H)2

RDS(ON)

where:

PRMS(H) = switching MOSFET conduction losses;

IRMS(H) = maximum switching MOSFET RMS current;

RDS(ON) = FET drain−to−source on−resistance.

Upper MOSFET switching losses occur during MOSFET

switch−on and switch−off, and can be calculated by:

PSWH + PSWH(ON) ) PSWH(OFF)

+

VIN

IOUT

(tRISE ) tFALL)

6T

where:

PSWH(ON) = upper MOSFET switch−on losses;

PSWH(OFF) = upper MOSFET switch−off losses;

VIN = input voltage;

IOUT = load current;

TRISE =MOSFET rise time (from FET manufacturer’s

switching characteristics performance curve);

TFALL = MOSFET fall time (from FET manufacturer’s

switching characteristics performance curve);

T = 1/fSW = period.

The total power dissipation in the switching MOSFET can

then be calculated as:

PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)

where:

PHFET(TOTAL) = total switching (upper) MOSFET losses;

PRMS(H) = upper MOSFET switch conduction Losses;

PSWH(ON) = upper MOSFET switch−on losses;

PSWH(OFF) = upper MOSFET switch−off losses.

Once the total power dissipation in the switching FET is

known, the maximum FET switch junction temperature can

be calculated:

TJ + TA ) [PHFET(TOTAL)

R

qJA]

where:

TJ = FET junction temperature;

TA = ambient temperature;

PHFET(TOTAL) = total switching (upper) FET losses;

RqJA = upper FET junction−to−ambient thermal

resistance.

Synchronous (Lower) FET Selection

The switch conduction losses for the lower FET are

calculated as follows:

PRMS(L) + IRMS2

RDS(ON)

+ IOUT

(1

* D) 2

RDS(ON)

where:

PRMS(L) = lower MOSFET conduction losses;

IOUT = load current;

D = Duty Cycle;

RDS(ON) = lower FET drain−to−source on−resistance.

The synchronous MOSFET has no switching losses,

except for losses in the internal body diode, because it turns

on into near zero voltage conditions. The MOSFET body

diode will conduct during the non−overlap time and the

resulting power dissipation (neglecting reverse recovery

losses) can be calculated as follows:

PSWL + VSD

ILOAD

non−overlap time

fSW

where:

PSWL = lower FET switching losses;

VSD = lower FET source−to−drain voltage;

ILOAD = load current;

Non−overlap time = GATE(L)−to−GATE(H) or

GATE(H)−to−GATE(L) delay

(from NCP5425 data sheet

Electrical Characteristics section);

fSW = switching frequency.

The total power dissipation in the synchronous (lower)

MOSFET can then be calculated as:

PLFET(TOTAL) + PRMS(L) ) PSWL

where:

PLFET(TOTAL) = Synchronous (lower) FET total losses;

PRMS(L) = Switch Conduction Losses;

PSWL = Switching losses.

Once the total power dissipation in the synchronous FET

is known the maximum FET switch junction temperature

can be calculated:

TJ + TA ) [PLFET(TOTAL)

R

qJA]

where:

TJ = MOSFET junction temperature;

TA = ambient temperature;

PLFET(TOTAL) = total synchronous (lower) FET losses;

RqJA = lower FET junction−to−ambient thermal

resistance.

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