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NCP5425DBR2G Datasheet(PDF) 12 Page - ON Semiconductor |
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NCP5425DBR2G Datasheet(HTML) 12 Page - ON Semiconductor |
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12 / 22 page  NCP5425 http://onsemi.com 12 Figure 8A − Basic Current Sensing Represents a basic inductor sensing configuration. When the voltage at pin +Is exceeds the voltage at pin –Is by 70 mV (nominal), the internal current sense comparator offset will be overcome. For this case, the current limit threshold is equal to (70 mV/Rx) amps. An obvious disadvantage of the basic configuration is the power supply designer has no control over the 70 mV offset, and limited control over the value of Rx. Therefore, he or she has little flexibility to set a specific current limit. Configurations (8B) and (8D) depict techniques to increase and decrease, respectively, the threshold current. Figure 8B – Increasing the Current Threshold Addition of resistor R2 forms a voltage divider such that only a portion of the voltage across Rx appears across C1. If, for example, R1 = R2, it will require a 140 mV drop across Rx to overcome the internal 70 mV current sense comparator offset. For optimum compensation with this configuration, R1 and R2 should be selected such that Rx is equal to their equivalent parallel resistance. Figure 8C – Bias Current Compensation Configurations 8A, 8B and 8D all introduce a potential error, since the bias currents of the current sense comparator inputs flow through unbalanced resistance paths. The addition of R3 in configuration 8C, where R3 = R1, restores a balanced input resistance, such that any voltage drops introduced by bias currents will cancel (assuming the +Is and –Is bias currents are equal). In the case of configuration 8B, R3 would be made equal to the equivalent resistance of R1 and R2 in parallel. Figure 8D – Decreasing the Current Threshold A voltage divider comprised of R3 and R4 is introduced to develop, by scaling the output voltage, a small voltage drop across R3 that opposes the internal current sense comparator offset. For example, if Vout = 1.2 V, R3 = 200 W, and R4 = 11.8 K, a DC voltage drop of 20 mV will be established across R3. The polarity of that voltage is such that it opposes the internal 70 mV offset, effectively reducing it to 50 mV. The current threshold is now given by (50 mV/Rx) instead of (70 mV/Rx). Current Limiting Both channels of the NCP5425 employ identical Cycle−by−Cycle current limiting. Comparators with internal 70 mV offsets provide the references for setting current limit. Once a voltage greater than 70 mV is applied to the current limiting comparator, it resets that channel’s output RS flip flop. This terminates the PWM pulse for the cycle and limits the energy delivered to the load. One advantage of this current limiting scheme is that the NCP5425 will limit large transient currents yet resume normal operation on the following cycle. A second benefit of limiting the PWM pulse width is, in an input power sharing application, one controller can be current limiting while the other supplies the remaining load current. Output Enable On/Off control of the regulator outputs can be implemented by pulling the COMP pins low. Driving the COMP pins below the 0.20 V PWM comparator offset voltage disables switching of the GATE drivers. |
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