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NCP5425DBR2G Datasheet(PDF) 9 Page - ON Semiconductor |
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NCP5425DBR2G Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 22 page ![]() NCP5425 http://onsemi.com 9 output voltage exceeds the COMP pin voltage, minus the 0.3 V PWM comparator offset threshold and the artificial ramp, the PWM comparator terminates the initial pulse. Figure 4. Idealized Startup Waveforms 4.2 V 0.3 V GATE(H)1 GATE(H)2 UVLO STARTUP NORMAL OPERATION VIN VCOMP VFB ts Normal Operation During normal operation, the duty cycle remains approximately constant as the V2 control loop maintains regulated output voltage under steady state conditions. Variations in supply line or output load conditions will result in changes in duty cycle to maintain regulation. Gate Charge Effect on Switching Times When using the on board gate drivers, the gate charge has an important effect on the switching times of the FETs. A finite amount of time is required to charge the effective capacitor seen at the gate of the FET. Therefore, the rise and fall times rise linearly with increased capacitive loading, according to the following graphs. Figure 5. Average Rise and Fall Times 02 80 60 40 20 0 LOAD (nF) Average Fall Time 90 03 5 46 8 7 70 50 30 10 Average Rise Time Transient Response The 200 ns reaction time of the control loop provides fast transient response to any variations in input voltage or output current. Pulse−by−pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitors during the time required to slew the inductor current. For better transient response, a combination of several high frequency and bulk output capacitors are typically used. Out−of−Phase Synchronization The turn−on of the second channel is delayed by half the switching cycle. This delay is supervised by the oscillator, which supplies a clock signal to the second channel that is 180 ° out of phase with the clock signal of the first channel. Advantages of out−of−phase synchronization are many. Since the input current pulses are interleaved with one another, the overlap time is reduced. Overlap reduction reduces the input filter requirement, allowing the use of smaller components. In addition, since peak current occurs during a shorter time period, emitted EMI is also reduced, potentially reducing shielding requirements. Interleaving the phases in a two phase application reduces ripple voltage and allows supplies with tighter tolerances to be built. Overvoltage Protection Overvoltage Protection (OVP) is provided as a consequence of the normal operation of the V2 control method, and requires no additional external components to implement. The control loop responds to an overvoltage condition within 200 ns, turning off the upper MOSFET and disconnecting the regulator from its input voltage. This results in a crowbar action to clamp the output voltage, preventing damage to the load. The regulator remains in this state until the overvoltage condition clears. Low Noise Disable Mode A PWM converter operating at a constant frequency concentrates its noise output over a small frequency band. In noise−sensitive applications, this frequency can be chosen to prevent interference with other system functions. Some applications may have even more stringent requirements, where absolutely no noise may be emitted for a short period of time. The user may disable the clock during noise sensitive periods to temporarily inhibit switching noise by disconnecting or pulling the ROSC pin to 3.3 V. This disables both gate drivers, leaving the switch node floating, and discharges the internal ramp. The control circuitry remains enabled while the clock and drivers are disabled, so the COMP pins will charge up to a higher voltage. The COMP pins are clamped to prevent excessive overshoot when switching is resumed. |
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