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NCP5425DBR2G Datasheet(PDF) 7 Page - ON Semiconductor |
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NCP5425DBR2G Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 22 page NCP5425 http://onsemi.com 7 GATE(H)2 GATE(L)2 VCC Figure 2. Block Diagram LNDM BST LNDM R S Reset Dominant Q Q CLK2 + − IS+2 IS−2 − + 70 mV OC2 + − − + 70 mV OC1 + − PWM COMP2 EA2 3.1 V + RAMP2 0.3 V VCC LNDM LNDM R S Reset Dominant Q Q CLK1 + − + − PWM COMP1 − EA1 + − 3.1 V + RAMP1 0.3 V UVLO BST GATE(L)1 COMP1 CLAMP REFERENCE UVLO 0.8 V COMP2 VREF2 VFB2 COMP1 VFB1 + − UVLO 4.2 V 4.0 V VCC OSCILLATOR AND RAMP CURRENT GENERATOR IRAMP1 IRAMP2 CLK1 CLK2 LNDM Low noise disable mode (pull ROSC high to activate) REFERENCE AND BIAS 3.1 V 0.8 V ROSC 3.1 V IRAMP1 RAMP1 3.1 V IRAMP2 RAMP2 S/D 3.1 V COMP2 CLAMP REFERENCE 3.1 V 3.1 V MODE Single or dual output mode GND GATE(H)1 IS+1 IS−1 + −− + − − + − + |
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