20

ATmega64(L)

2490LS–AVR–10/06

5.

Updated code example in “WDTCR – Watchdog Timer Control Register” on

page 58.

6.

Added section “Unconnected Pins” on page 72.

7.

Updated Table 19 on page 53, Table 20 on page 57, Table 95 on page 238, and

Table 60 on page 136.

8.

Updated Figure 116 on page 241.

9.

Updated “Version” on page 257.

10. Updated “DC Characteristics” on page 328.

11. Updated “Typical Characteristics” on page 343.

12. Updated features in“Analog to Digital Converter” on page 232 and Table 136

on page 336.

13. Updated “Ordering Information” on page 14.

Changes from Rev.

2490F-12/03 to Rev.

2490G-03/04

1.

Updated “Errata” on page 17.

Changes from Rev.

2490E-09/03 to Rev.

2490F-12/03

1.

Updated “Calibrated Internal RC Oscillator” on page 43.

Changes from Rev.

2490D-02/03 to Rev.

2490E-09/03

1.

Updated note in “XDIV – XTAL Divide Control Register” on page 39.

2.

Updated “JTAG Interface and On-chip Debug System” on page 51.

3.

Updated “TAP – Test Access Port” on page 250 regarding JTAGEN.

4.

Updated description for the JTD bit on page 260.

5.

Added a note regarding JTAGEN fuse to Table 118 on page 294.

6.

Updated R

7.

Updated “ADC Characteristics” on page 335.

8.

Added a proposal for solving problems regarding the JTAG instruction

IDCODE in “Errata” on page 17.

Changes from Rev.

2490C-09/02 to Rev.

2490D-02/03

1.

Added reference to Table 124 on page 298 from both SPI Serial Programming

and Self Programming to inform about the Flash page size.

2.

Added Chip Erase as a first step under “Programming the Flash” on page 325

and “Programming the EEPROM” on page 326.