17

ATmega64(L)

2490LS–AVR–10/06

Errata

The revision letter in this section refers to the revision of the ATmega64 device.

ATmega64, rev. A to C

1.

First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V

sion will take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Com-

parator before the first conversion.

2.

Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare

Register, OCR2

3.

Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV

register, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency

change. Thus, the next 8 instructions after the change should be NOP instructions.

To ensure this, follow this procedure:

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

Assembly Code Example:

CLI

; clear global interrupt enable

OUT

XDIV, temp

; set new prescale value

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

SEI

; clear global interrupt enable