 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT45DB081A Datasheet(PDF) 4 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT45DB081A Datasheet(HTML) 4 Page - ATMEL Corporation |
|
|
4 / 28 page  AT45DB081A 4 The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits and the read- ing of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. BURST ARRAY READ: The Burst Array Read operation functions almost identically to the Continuous Array Read operation but allows much higher read throughputs by uti- lizing faster clock frequencies. The Burst Array Read command allows the device to burst an entire page of data out at the maximum SCK frequency defined by the f BAR parameter. Differences between the Burst Array Read and Continuous Array Read operations are limited to timing only. The opcodes utilized and the opcode and addressing sequence for the Burst Array Read are identical to the Con- tinuous Array Read. The opcode of 68H or E8H must be clocked into the device followed by the 24 address bits and 32 don’t care bits. Following the 32 don’t care bits, addi- tional clock pulses on the SCK pin will result in serial data being output on the SO (serial output) pin. As with the Continuous Array Read, the CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits and the reading of data. During a Burst Array Read, when the end of a page in main memory is reached (the last bit of the page has been clocked out), the system must delay the next SCK pulse by a minimum time of t BRBD. This delay is necessary to allow the device enough time to cross over the burst read boundary, which is defined as the end of one page in memory to the begin- ning of the next page. When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. The transition from the last bit of the array back to the beginning of the array is also considered a burst read boundary. Therefore, the system must delay the SCK pulse that will be used to read the first bit of the memory array by a minimum time of t BRBD. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. The maximum SCK frequency allowable for the Burst Array Read is defined by the fBAR specification. The Burst Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data directly from any one of the 4096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device followed by 24 address bits and 32 don’t care bits. The first three bits of the 24-bit address sequence are reserved bits, the next 12 address bits (PA11-PA0) specify the page address, and the next nine address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care bits which fol- low the 24 address bits are sent to initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits and the reading of data. When the end of a page in main memory is reached during a Main Memory Page Read, the device will continue reading at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the opcode must be followed by 15 don’t care bits, nine address bits, and eight don't care bits. Since the buffer size is 264-bytes, nine address bits (BFA8-BFA0) are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits and the read- ing of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. STATUS REGISTER READ: The status register can be used to determine the device’s Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation or the device density. To read the status register, an opcode of 57H or D7H must be loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five most-significant bits of the status register will con- tain device information, while the remaining three least- significant bits are reserved for future use and will have undefined values. After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so each repeating sequence will output new data. |
Similar Part No. - AT45DB081A |
|
Similar Description - AT45DB081A |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
