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TMP411 Datasheet(PDF) 16 Page - Burr-Brown (TI) |
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TMP411 Datasheet(HTML) 16 Page - Burr-Brown (TI) |
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16 / 25 page  TMP411 SBOS383A − FEBRUARY 2007 www.ti.com 16 When reading from the TMP411, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer Register. This transaction is accomplished by issuing a slave address byte with the R/W bit low, followed by the Pointer Register byte. No additional data is required. The master can then generate a START condition and send the slave address byte with the R/W bit high to initiate the read command. See Figure 15 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually send the Pointer Register bytes, because the TMP411 retains the Pointer Register value until it is changed by the next write operation. Note that register bytes are sent MSB first, followed by the LSB. TIMING DIAGRAMS The TMP411 is Two-Wire and SMBus-compatible. Figure 13 to Figure 16 describe the various operations on the TMP411. Bus definitions are given below. Parameters for Figure 13 are defined in Table 12. Bus Idle: Both SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a STOP condition. Each data transfer terminates with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, data transfer termination can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave. SCL SDA t (LOW) t R t F t (HDSTA) t (HDSTA) t (HDDAT) t (B U F) t (SUDAT) t (HIGH) t (SUSTA) t (SUSTO) PS SP Figure 13. Two-Wire Timing Diagram |
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