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5CEFA5F23A6ES Datasheet(PDF) 35 Page - Intel Corporation

Part # 5CEFA5F23A6ES
Description  Cyclone V Device Overview
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

5CEFA5F23A6ES Datasheet(HTML) 35 Page - Intel Corporation

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Date
Version
Changes
July 2014
2014.07.07
Updated the I/O vertical migration figure to clarify the migration capability of
Cyclone V SE and SX devices.
December 2013
2013.12.26
• Corrected single or dual-core ARM Cortex-A9 MPCore processor-up to 925
MHz from 800 MHz.
• Removed "Preliminary" texts from Ordering Code figures, Maximum
Resources, Package Plan and I/O Vertical Migration tables.
• Removed the note "The number of GPIOs does not include transceiver
I/Os. In the Quartus II software, the number of user I/Os includes
transceiver I/Os." for GPIOs in the Maximum Resource Counts table for
Cyclone V E and SE.
• Added link to Altera Product Selector for each device variant.
• Updated Embedded Hard IPs for Cyclone V GT devices to indicate
Maximum 2 hard PCIe and 2 hard memory controllers.
• Added leaded package options.
• Removed the note "The number of PLLs includes general-purpose
fractional PLLs and transceiver fractional PLLs." for all PLLs in the
Maximum Resource Counts table.
• Corrected max LVDS counts for transmitter and receiver for Cyclone V E
A5 device from 84 to 60.
• Corrected max LVDS counts for transmitter and receiver for Cyclone V E
A9 device from 140 to 120.
• Corrected variable-precision DSP block, 27 x 27 multiplier, 18 x 18
multiplier adder mode and 18 x 18 multiplier adder summed with 36 bit
input for Cyclone V SE devices from 58 to 84.
• Corrected 18 x 18 multiplier for Cyclone V SE devices from 116 to 168.
• Corrected 9 x 9 multiplier for Cyclone V SE devices from 174 to 252.
• Corrected LVDS transmitter for Cyclone V SE A2 and A4 as well as SX C2
and C4 devices from 31 to 32.
• Corrected LVDS receiver for Cyclone V SE A2 and A4 as well as SX C2 and
C4 devices from 35 to 37.
• Corrected transceiver speed grade for Cyclone V ST devices ordering code
from 4 to 5.
• Updated the DDR3 SDRAM for the maximum frequency's soft controller
and the minimum frequency from 300 to 303 for voltage 1.35V.
• Added links to Altera's External Memory Spec Estimator tool to the topics
listing the external memory interface performance.
• Corrected XAUI is supported through the soft PCS in the PCS features for
Cyclone V.
• Added decompression support for the CvP configuration mode.
May 2013
2013.05.06
• Added link to the known document issues in the Knowledge Base.
• Moved all links to the Related Information section of respective topics for
easy reference.
• Corrected the title to the PCIe hard IP topic. Cyclone V devices support
only PCIe Gen1 and Gen2.
• Updated Supporting Feature in Table 1 of Increased bandwidth capacity to
'6.144 Gbps'.
• Updated Description in Table 2 of Low-power high-speed serial interface to
'6.144 Gbps'.
• Updated Description in Table 3 of Cyclone V GT to '6.144 Gbps'.
• Updated the M386 package to M383 for Figure 1, Figure 2 and Figure 3.
• Updated Figure 2 and Figure 3 for Transceiver Count by adding 'F : 4'.
• Updated LVDS in the Maximum Resource Counts tables to include
Transmitter and Receiver values.
• Updated the package plan with M383 for the Cyclone V E device.
• Removed the M301 and M383 packages from the Cyclone V GX C4 device.
• Updated the GPIO count to '129' for the M301 package of the Cyclone V
GX C5 device.
• Updated 5 Gbps to '6.144 Gbps' forCyclone V GT device.
continued...
Cyclone V Device Overview
683694 | 2018.05.07
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Cyclone V Device Overview
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