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5CEFA5F23A6ES Datasheet(PDF) 29 Page - Intel Corporation

Part # 5CEFA5F23A6ES
Description  Cyclone V Device Overview
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

5CEFA5F23A6ES Datasheet(HTML) 29 Page - Intel Corporation

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Figure 11.
HPS with Dual-Core Arm Cortex-A9 MPCore Processor
FPGA Fabric
HPS
HPS-to-FPGA
Lightweight
HPS-to-FPGA
FPGA-to-HPS
FPGA-to-HPS SDRAM
Configuration
Controller
FPGA
Manager
64 KB
On-Chip RAM
64 KB
Boot ROM
Level 3
Interconnect
Ethernet
MAC (2x)
USB
OTG (2x)
NAND Flash
Controller
SD/MMC
Controller
DMA
Controller
STM
ETR
(Trace)
Debug
Access Port
ARM Cortex-A9 MPCore
MPU Subsystem
CPU0
ARM Cortex-A9
with NEON/FPU,
32 KB Instruction Cache,
32 KB Data Cache, and
Memory Management
Unit
CPU1
ARM Cortex-A9
with NEON/FPU,
32 KB Instruction Cache,
32 KB Data Cache, and
Memory Management
Unit
SCU
ACP
Level 2 Cache (512 KB)
Multiport
DDR SDRAM
Controller
with
Optional ECC
Peripherals
(UART, Timer, I2C, Watchdog Timer, GPIO, SPI, Clock Manager, Reset Manager, Scan Manager, System Manager, and Quad
SPI Flash Controller)
System Peripherals and Debug Access Port
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module
has an integrated DMA controller. For modules without an integrated DMA controller,
an additional DMA controller module provides up to eight channels of high-bandwidth
data transfers. Peripherals that communicate off-chip are multiplexed with other
peripherals at the HPS pin level. This allows you to choose which peripherals to
interface with other devices on your PCB.
The debug access port provides interfaces to industry standard JTAG debug probes
and supports Arm CoreSight debug and core traces to facilitate software development.
Cyclone V Device Overview
683694 | 2018.05.07
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Cyclone V Device Overview
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