![]() |
Electronic Components Datasheet Search |
|
5CEFA5F23A6ES Datasheet(PDF) 23 Page - Intel Corporation |
|
|
5CEFA5F23A6ES Datasheet(HTML) 23 Page - Intel Corporation |
23 / 37 page ![]() PLL Features The PLLs in the Cyclone V devices support the following features: • Frequency synthesis • On-chip clock deskew • Jitter attenuation • Programmable output clock duty cycles • PLL cascading • Reference clock switchover • Programmable bandwidth • User-mode reconfiguration of PLLs • Low power mode for each fractional PLL • Dynamic phase shift • Direct, source synchronous, zero delay buffer, external feedback, and LVDS compensation modes Fractional PLL In addition to integer PLLs, the Cyclone V devices use a fractional PLL architecture. The devices have up to eight PLLs, each with nine output counters. You can use the output counters to reduce PLL usage in two ways: • Reduce the number of oscillators that are required on your board by using fractional PLLs • Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency synthesis—removing the need for off-chip reference clock sources in your design. The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric. FPGA General Purpose I/O Cyclone V devices offer highly configurable GPIOs. The following list describes the features of the GPIOs: • Programmable bus hold and weak pull-up • LVDS output buffer with programmable differential output voltage (VOD ) and programmable pre-emphasis • On-chip parallel termination (RT OCT) for all I/O banks with OCT calibration to limit the termination impedance variation • On-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity • Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop (DLL) delay chain with fine and coarse architecture Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview 23 |
Similar Part No. - 5CEFA5F23A6ES |
|
Similar Description - 5CEFA5F23A6ES |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |