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5CEFA5F23A6ES Datasheet(PDF) 18 Page - Intel Corporation |
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5CEFA5F23A6ES Datasheet(HTML) 18 Page - Intel Corporation |
18 / 37 page ![]() I/O Vertical Migration for Cyclone V Devices Figure 7. Vertical Migration Capability Across Cyclone V Device Packages and Densities The arrows indicate the vertical migration paths. The devices included in each vertical migration path are shaded. You can also migrate your design across device densities in the same package option if the devices have the same dedicated pins, configuration pins, and power pins. Variant Member Code Package M301 M383 M484 F256 U324 U484 F484 U672 F672 F896 F1152 Cyclone V E A2 A4 A5 A7 A9 Cyclone V GX C3 C4 C5 C7 C9 Cyclone V GT D5 D7 D9 Cyclone V SE A2 A4 A5 A6 Cyclone V SX C2 C4 C5 C6 Cyclone V ST D5 D6 You can achieve the vertical migration shaded in red if you use only up to 175 GPIOs for the M383 package, and 138 GPIOs for the U672 package. These migration paths are not shown in the Intel Quartus Prime software Pin Migration View. Note: To verify the pin migration compatibility, use the Pin Migration View window in the Intel Quartus Prime software Pin Planner. Adaptive Logic Module Cyclone V devices use a 28 nm ALM as the basic building block of the logic fabric. The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than previous generations. Cyclone V Device Overview 683694 | 2018.05.07 Cyclone V Device Overview Send Feedback 18 |
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