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5CEFA5F23A6ES Datasheet(PDF) 15 Page - Intel Corporation

Part # 5CEFA5F23A6ES
Description  Cyclone V Device Overview
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

5CEFA5F23A6ES Datasheet(HTML) 15 Page - Intel Corporation

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Resource
Member Code
C2
C4
C5
C6
HPS PLL
3
3
3
3
3 Gbps Transceiver
6
6
9
9
FPGA GPIO (8)
145
145
288
288
HPS I/O
181
181
181
181
LVDS
Transmitter
32
32
72
72
Receiver
37
37
72
72
PCIe Hard IP Block
2
2
2 (9)
2 (9)
FPGA Hard Memory Controller
1
1
1
1
HPS Hard Memory Controller
1
1
1
1
Arm Cortex-A9 MPCore Processor
Dual-core
Dual-core
Dual-core
Dual-core
Related Information
True LVDS Buffers in Devices, I/O Features in Cyclone V Devices
Provides the number of LVDS channels in each device package.
Package Plan
Table 13.
Package Plan for Cyclone V SX Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific
I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
Member Code
U672
(23 mm)
F896
(31 mm)
FPGA GPIO
HPS I/O
XCVR
FPGA GPIO
HPS I/O
XCVR
C2
145
181
6
C4
145
181
6
C5
145
181
6
288
181
9
C6
145
181
6
288
181
9
Cyclone V ST
This section provides the available options, maximum resource counts, and package
plan for the Cyclone V ST devices.
The information in this section is correct at the time of publication. For the latest
information and to get more details, refer to the Product Selector Guide.
(8) The number of GPIOs does not include transceiver I/Os. In the Intel Quartus Prime software,
the number of user I/Os includes transceiver I/Os.
(9) 1 PCIe Hard IP Block in U672 package.
Cyclone V Device Overview
683694 | 2018.05.07
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Cyclone V Device Overview
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