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FIN1001 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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FIN1001 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page ![]() © 2004 Fairchild Semiconductor Corporation DS500721 www.fairchildsemi.com December 2001 Revised August 2004 FIN1001 3.3V LVDS 1-Bit High Speed Differential Driver General Description This single driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technol- ogy. The driver translates LVTTL signal levels to LVDS lev- els with a typical differential output swing of 350 mV which provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed trans- fer of clock or data. The FIN1001 can be paired with its companion receiver, the FIN1002, or with any other LVDS receiver. Features s Greater than 600Mbs data rate s 3.3V power supply operation s 0.5ns maximum differential pulse skew s 1.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout s 5-Lead SOT23 package saves space Ordering Code: Pin Descriptions Function Table H = HIGH Logic Level L = LOW Logic Level Connection Diagram Pin Assignment for SOT23 (Top View) Order Number Package Number Package Description FIN1001M5 MA05B 5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel] FIN1001M5X MA05B 5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel] Pin Name Description DIN LVTTL Data Input DOUT+ Non-inverting LVDS Driver Output DOUT− Inverting LVDS Driver Output VCC Power Supply GND Ground NC No Connect Input Outputs DIN DOUT+ DOUT− LL H HH L |
Similar Part No. - FIN1001_04 |
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Similar Description - FIN1001_04 |
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