CDCL6010 datasheet(14/24 Pages) TI

Part #	CDCL6010

Description	1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer

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Manufacturer	TI [Texas Instruments]

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CDCL6010

SLLS780 – FEBRUARY 2007

Power Up

Bit

Bit Name

Description/Function

Type

Condition

Reference To

7

ENDRV3

YP[3], YN[3] enable; if 0 output is disabled

R/W

1

6

ENDRV2

YP[2], YN[2] enable; if 0 output is disabled

R/W

1

5

ENDRV1

YP[1], YN[1] enable; if 0 output is disabled

R/W

1

4

ENDRV0

YP[0], YN[0] enable; if 0 output is disabled

R/W

1

3

SELBW[3]

PLL BW select; if 1 external loop filter is expected

R/W

0

Table 6

2

SELBW[2]

PLL BW select; if 1 external loop filter is expected

R/W

0

Table 6

1

SELBW[1]

PLL BW select; if 1 external loop filter is expected

R/W

0

Table 6

0

SELBW[0]

PLL BW select; if 1 external loop filter is expected

R/W

0

Table 6

Bit

Power Up

Bit

Name

Description/Function

Type

Condition

Reference To

7

ENPLL

PLL enable; if 0 PLL is switched off

R/W

1

6

RES

Reserved

R/W

0

5

SELM[1]

Divide ratio select for input clock CLKP and CLKN

R/W

0

Table 3

4

SELM[0]

Divide ratio select for input clock CLKP and CLKN

R/W

0

Table 3

3

SELN[3]

Divide ratio select for pre-divider N (PLL clock)

R/W

1

Table 2

2

SELN[2]

Divide ratio select for pre-divider N (PLL clock)

R/W

0

Table 2

1

SELN[1]

Divide ratio select for pre-divider N (PLL clock)

R/W

0

Table 2

0

SELN[0]

Divide ratio select for pre-divider N (PLL clock)

R/W

1

Table 2

14

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