CDCL6010 datasheet(12/24 Pages) TI | 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer

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CDCL6010 Datasheet(PDF) 12 Page - Texas Instruments

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Part #	CDCL6010

Description	1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer

Download	24 Pages

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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SDA/SCL Bus Configuration Command Bitmap

Byte 0:

Byte 1:

Byte 2:

CDCL6010

SLLS780 – FEBRUARY 2007

Word Write Programming Sequence:

1

7

1

1

8

1

8

1

8

1

1

S

Slave Address

Wr

A

Command Code

A

Data Byte Low

A

Data Byte High

A

P

Word Read Programming Sequence:

1

7

1

1

8

1

1

7

1

1

8

1

8

1

1

Slave

Command

Slave

S

Wr

A

A

S

Rd

A

Data Byte

A

Data Byte

N

P

Address

Code

Address

Power Up

Bit

Bit Name

Description/Function

Type

Condition

Reference To

7

PLL-LOCK

1 if PLL has achieved lock, otherwise 0

R

0

6

MANF[6]

Manufacturer reserved

R

5

MANF[5]

Manufacturer reserved

R

4

MANF[4]

Manufacturer reserved

R

3

MANF[3]

Manufacturer reserved

R

2

MANF[2]

Manufacturer reserved

R

1

MANF[1]

Manufacturer reserved

R

0

MANF[0]

Manufacturer reserved

R

Power Up

Bit

Bit Name

Description/Function

Type

Condition

Reference To

7

RES

Reserved

R/W

0

6

RES

Reserved

R/W

0

5

ENPH

Phase select enable

R/W

1

4

PH1[4]

Phase select for YP[9:5] and YN[9:5]

R/W

0

Table 4, Table 5

3

PH1[3]

Phase select for YP[9:5] and YN[9:5]

R/W

0

Table 4, Table 5

2

PH1[2]

Phase select for YP[9:5] and YN[9:5]

R/W

0

Table 4, Table 5

1

PH1[1]

Phase select for YP[9:5] and YN[9:5]

R/W

0

Table 4, Table 5

0

PH1[0]

Phase select for YP[9:5] and YN[9:5]

R/W

0

Table 4, Table 5

Power Up

Bit

Bit Name

Description/Function

Type

Condition

Reference To

7

RES

Reserved

R/W

0

6

RES

Reserved

R/W

0

5

ENP1

Post-divider P1 enable; if 0 output YP[9:5] and YN[9:5] are disabled

R/W

1

4

ENBP1

Bypass PLL for post-divider P1: If 1 input is CLKP/CLKN, if 0 input is PLL

R/W

0

clock

3

SELP1[3]

Divide ratio select for post-divider P1

R/W

0

Table 1

2

SELP1[2]

Divide ratio select for post-divider P1

R/W

1

Table 1

1

SELP1[1]

Divide ratio select for post-divider P1

R/W

1

Table 1

0

SELP1[0]

Divide ratio select for post-divider P1

R/W

1

Table 1

12

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