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AC ELECTRICAL CHARACTERISTICS FOR THE SDA/SCL INTERFACE

(1)

CDCL6010

SLLS780 – FEBRUARY 2007

AC ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating conditions (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Residual clock output jitter

400kHz PLL bandwidth

10Hz–1MHz offset

2.01

ps RMS

1MHz–20MHz offset

0.45

ps RMS

12kHz–20MHz offset

2.11

ps RMS

Input-to-output delay

3

ns

YP[9:0] outputs, PLL bypass mode

150

ps

YP[9:0] outputs, PLL mode

Clock output skew

–64

64

ps

YP[9:0] outputs relative to YP[0]

45

55

%

(1)

Output duty cycle of the bypass output and for post-divide ratio = 1 is just as good as the input duty cycle.

PARAMETER

MIN

TYP

MAX

UNIT

SCL frequency

400

kHz

START hold time

0.6

µs

SCL low-pulse duration

1.3

µs

SCL high-pulse duration

0.6

µs

START setup time

0.6

µs

SDA hold time

0

µs

SDA setup time

0.6

µs

SCL / SDA input rise time

0.3

µs

SCL / SDA input fall time

0.3

µs

STOP setup time

0.6

µs

Bus free time

1.3

µs

(1)

See Figure 4 for the timing behavior.

5

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