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CDCL6010 Datasheet(PDF) 4 Page - Texas Instruments |
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CDCL6010 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 24 page ![]() www.ti.com DC ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS CDCL6010 SLLS780 – FEBRUARY 2007 Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDD Total current from digital 1.8V supply All outputs enabled; VDD = VDD,typ 270 mA 30.72MHz input; 61.44MHz output IAVDD Total current from analog 1.8V supply All outputs enabled; AVDD = VDD,typ 85 mA 30.72MHz input; 61.44MHz output VIL,CMOS Low level CMOS input voltage VDD = 1.8V –0.2 0.6 V VIH,CMOS High level CMOS input voltage VDD = 1.8V VDD– 0.6 VDD V IIL,CMOS Low level CMOS input current VDD = VDD,max, VIL = 0.0V –120 µA IIH,CMOS High level CMOS input current VDD = VDD,max, VIH = 1.9V 65 µA VOL,SDA Low level CMOS output voltage for the Sink current = 3mA 0 0.2VDD V SDA pin IOL,CMOS Low level CMOS output current 8 mA Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential input impedance for the LVDS input ZD,IN 90 132 Ω terminals VCM,IN Common-mode voltage, LVDS input 1125 1200 1375 mV VS,IN Single-ended LVDS input voltage swing 100 600 mVPP VD,IN Differential LVDS input voltage swing 200 1200 mVPP tR,OUT, Output signal rise/fall time 20%–80% 100 ps tF,OUT VCM,OUT Common-mode voltage, CML outputs VDD –0.31 VDD –0.23 VDD –0.19 V VS,OUT Single-ended CML output voltage swing ac-coupled 180 230 280 mVPP VD,OUT Differential CML output voltage swing ac-coupled 360 460 560 mVPP FIN Clock input frequency 30 319 MHz FOUT Clock output frequency 15 1250 MHz LOUT Residual clock output phase noise FIN = 30.72MHz , FOUT = 61.44MHz 400kHz PLL bandwidth at 10Hz offset –103 dBc/Hz at 100Hz offset –114 dBc/Hz at 1kHz offset –123 dBc/Hz at 10kHz offset –121 dBc/Hz at 100kHz offset –119 dBc/Hz at 1MHz offset –138 dBc/Hz at 10MHz offset –152 dBc/Hz at 20MHz offset –152 dBc/Hz 4 Submit Documentation Feedback |
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