ep1c12f100i8es datasheet(4/104 Pages) ALTERA

Part #	EP1C12F100I8ES

Description	Cyclone FPGA Family Data Sheet

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Manufacturer	ALTERA [Altera Corporation]

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Altera Corporation

Preliminary

January 2007

Cyclone Device Handbook, Volume 1

Features

The Cyclone device family offers the following features:

■

2,910 to 20,060 LEs, see Table 1–1

■

Up to 294,912 RAM bits (36,864 bytes)

■

Supports configuration through low-cost serial configuration device

■

Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■

Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■

High-speed (640 Mbps) LVDS I/O support

■

Low-speed (311 Mbps) LVDS I/O support

■

311-Mbps RSDS I/O support

■

Up to two PLLs per device provide clock multiplication and phase

shifting

■

Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■

Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■

Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions.

Table 1–1. Cyclone Device Features

Feature

EP1C3

EP1C4

EP1C6

EP1C12

EP1C20

LEs

2,910

4,000

5,980

12,060

20,060

M4K RAM blocks (128

× 36 bits)

1317205264

Total RAM bits

59,904

78,336

92,160

239,616

294,912

PLLs

12222

Maximum user I/O pins (1)

104

301

185

249

301

Note to Table 1–1:

(1)

This parameter includes global clock pins.

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