ep1c12f100i8es datasheet(95/104 Pages) ALTERA

Part #	EP1C12F100I8ES

Description	Cyclone FPGA Family Data Sheet

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Manufacturer	ALTERA [Altera Corporation]

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Altera Corporation

4–25

January 2007

Preliminary

Timing Model

1.5-V LVTTL

2 mA

6,789

7,807

8,825

ps

4 mA

5,109

5,875

6,641

ps

8 mA

4,793

5,511

6,230

ps

SSTL-3 class I

1,390

1,598

1,807

ps

SSTL-3 class II

989

1,137

1,285

ps

SSTL-2 class I

1,965

2,259

2,554

ps

SSTL-2 class II

1,692

1,945

2,199

ps

LVDS

802

922

1,042

ps

Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 1 of 2)

I/O Standard

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

LVCMOS

2 mA

1,800

2,070

2,340

ps

4 mA

1,311

1,507

1,704

ps

8 mA

945

1,086

1,228

ps

12 mA

807

928

1,049

ps

3.3-V LVTTL

4 mA

1,831

2,105

2,380

ps

8 mA

1,484

1,705

1,928

ps

12 mA

973

1,118

1,264

ps

16 mA

1,012

1,163

1,315

ps

24 mA

838

963

1,089

ps

2.5-V LVTTL

2 mA

2,747

3,158

3,570

ps

8 mA

1,757

2,019

2,283

ps

12 mA

1,763

2,026

2,291

ps

16 mA

1,623

1,865

2,109

ps

1.8-V LVTTL

2 mA

5,506

6,331

7,157

ps

8 mA

4,220

4,852

5,485

ps

12 mA

4,008

4,608

5,209

ps

1.5-V LVTTL

2 mA

6,789

7,807

8,825

ps

4 mA

5,109

5,875

6,641

ps

8 mA

4,793

5,511

6,230

ps

3.3-V PCI

923

1,061

1,199

ps

Table 4–44. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2)

I/O Standard

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

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