Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

EP1C12F100I8ES Datasheet(PDF) 43 Page - Altera Corporation

Part # EP1C12F100I8ES
Description  Cyclone FPGA Family Data Sheet
Download  104 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I8ES Datasheet(HTML) 43 Page - Altera Corporation

Back Button EP1C12F100I8ES Datasheet HTML 39Page - Altera Corporation EP1C12F100I8ES Datasheet HTML 40Page - Altera Corporation EP1C12F100I8ES Datasheet HTML 41Page - Altera Corporation EP1C12F100I8ES Datasheet HTML 42Page - Altera Corporation EP1C12F100I8ES Datasheet HTML 43Page - Altera Corporation EP1C12F100I8ES Datasheet HTML 44Page - Altera Corporation EP1C12F100I8ES Datasheet HTML 45Page - Altera Corporation EP1C12F100I8ES Datasheet HTML 46Page - Altera Corporation EP1C12F100I8ES Datasheet HTML 47Page - Altera Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 43 / 104 page
background image
Altera Corporation
2–37
January 2007
Preliminary
Global Clock Network & Phase-Locked Loops
does not have dedicated clock output pins. The EP1C6 device in the
144-pin TQFP package only supports dedicated clock outputs from
PLL 1.
Clock Feedback
Cyclone PLLs have three modes for multiplication and/or phase shifting:
Zero delay buffer mode
⎯The external clock output pin is phase-
aligned with the clock input pin for zero delay.
Normal mode
⎯If the design uses an internal PLL clock output, the
normal mode compensates for the internal clock delay from the input
clock pin to the IOE registers. The external clock output pin is phase
shifted with respect to the clock input pin if connected in this mode.
You defines which internal clock output from the PLL should be
phase-aligned to compensate for internal clock delay.
No compensation mode
⎯In this mode, the PLL will not compensate
for any clock networks.
Phase Shifting
Cyclone PLLs have an advanced clock shift capability that enables
programmable phase shifts. You can enter a phase shift (in degrees or
time units) for each PLL clock output port or for all outputs together in
one shift. You can perform phase shifting in time units with a resolution
range of 125 to 250 ps. The finest resolution equals one eighth of the VCO
period. The VCO period is a function of the frequency input and the
multiplication and division factors. Each clock output counter can choose
a different phase of the VCO period from up to eight taps. You can use this
clock output counter along with an initial setting on the post-scale
counter to achieve a phase-shift range for the entire period of the output
clock. The phase tap feedback to the m counter can shift all outputs to a
single phase. The Quartus II software automatically sets the phase taps
and counter settings according to the phase shift entered.
Lock Detect Signal
The lock output indicates that there is a stable clock output signal in
phase with the reference clock. Without any additional circuitry, the lock
signal may toggle as the PLL begins tracking the reference clock.
Therefore, you may need to gate the lock signal for use as a system-
control signal. For correct operation of the lock circuit below
–20 C, fIN/N > 200 MHz.


Similar Part No. - EP1C12F100I8ES

ManufacturerPart #DatasheetDescription
logo
Altera Corporation
EP1C12F100I8 ALTERA-EP1C12F100I8 Datasheet
1Mb / 94P
   Cyclone FPGA Family
More results

Similar Description - EP1C12F100I8ES

ManufacturerPart #DatasheetDescription
logo
Altera Corporation
EP1C12Q240C8N ALTERA-EP1C12Q240C8N Datasheet
1Mb / 106P
   Section I. Cyclone FPGA Family Data Sheet
EP1C12F256C8N ALTERA-EP1C12F256C8N Datasheet
1Mb / 106P
   Section I. Cyclone FPGA Family Data Sheet
EP1C20F ALTERA-EP1C20F Datasheet
1Mb / 106P
   Cyclone FPGA Family
EP1C20F400 ALTERA-EP1C20F400 Datasheet
1Mb / 94P
   Cyclone FPGA Family
EP4CE115F29I7N ALTERA-EP4CE115F29I7N Datasheet
372Kb / 14P
   Cyclone IV FPGA Device Family
EP4CE10E22C8N ALTERA-EP4CE10E22C8N Datasheet
498Kb / 14P
   Cyclone IV FPGA Device Family Overview
EP4CE6E22I7N ALTERA-EP4CE6E22I7N Datasheet
498Kb / 14P
   Cyclone IV FPGA Device Family Overview
EP4CE6E22C8 ALTERA-EP4CE6E22C8 Datasheet
498Kb / 14P
   Cyclone IV FPGA Device Family Overview
EP4CE55F29I7 ALTERA-EP4CE55F29I7 Datasheet
372Kb / 14P
   Cyclone IV FPGA Device Family Overview
logo
Xilinx, Inc
XC3SD3400A-5FG676C XILINX-XC3SD3400A-5FG676C Datasheet
2Mb / 101P
   Spartan-3A DSP FPGA Family Data Sheet
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com