EP1C12F100I8ES datasheet(34/104 Pages) ALTERA

Part #	EP1C12F100I8ES

Description	Cyclone FPGA Family Data Sheet

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Manufacturer	ALTERA [Altera Corporation]

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Altera Corporation

Preliminary

January 2007

Cyclone Device Handbook, Volume 1

Read/Write Clock Mode

The M4K memory blocks implement read/write clock mode for simple

dual-port memory. You can use up to two clocks in this mode. The write

clock controls the block's data inputs,

wraddress, and wren. The read

clock controls the data output,

rdaddress, and rden. The memory

blocks support independent clock enables for each clock and

asynchronous clear signals for the read- and write-side registers.

Figure 2–20 shows a memory block in read/write clock mode.

Figure 2–20. Read/Write Clock Mode in Simple Dual-Port Mode

Notes (1), (2)

Notes to Figure 2–20:

(1)

All registers shown except the rden register have asynchronous clear ports.

(2)

Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both

read and write operations.

6

D

ENA

Q

D

ENA

Q

D

ENA

Q

D

ENA

Q

D

ENA

Q

data[ ]

D

ENA

Q

wraddress[ ]

address[ ]

Memory Block

256

× 16

512

× 8

1,024

× 4

2,048

× 2

4,096

× 1

Data In

Read Address

Write Address

Write Enable

Read Enable

Data Out

rdclken

wrclken

wrclock

rdclock

wren

rden

6 LAB Row

Clocks

To MultiTrack

Interconnect

D

ENA

Q

byteena[ ]

Byte Enable

Write

Pulse

Generator

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