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EP1C12F100I8ES Datasheet(PDF) 12 Page - Altera Corporation |
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EP1C12F100I8ES Datasheet(HTML) 12 Page - Altera Corporation |
12 / 104 page ![]() 2–6 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 Figure 2–5. Cyclone LE Each LE's programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinatorial functions, the LUT output bypasses the register and drives directly to the LE outputs. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated labclk1 labclk2 labclr2 labpre/aload Carry-In1 Carry-In0 LAB Carry-In Clock & Clock Enable Select LAB Carry-Out Carry-Out1 Carry-Out0 Look-Up Table (LUT) Carry Chain Row, column, and direct link routing Row, column, and direct link routing Programmable Register PRN/ALD CLRN D Q ENA Register Bypass Packed Register Select Chip-Wide Reset labclkena1 labclkena2 Synchronous Load and Clear Logic LAB-wide Synchronous Load LAB-wide Synchronous Clear Asynchronous Clear/Preset/ Load Logic data1 data2 data3 data4 LUT chain routing to next LE labclr1 Local Routing Register chain output ADATA addnsub Register Feedback Register chain routing from previous LE |
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