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EP1C12F100I8ES Datasheet(PDF) 99 Page - Altera Corporation

Part # EP1C12F100I8ES
Description  Cyclone FPGA Family Data Sheet
Download  104 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I8ES Datasheet(HTML) 99 Page - Altera Corporation

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Altera Corporation
4–29
January 2007
Preliminary
Timing Model
PLL Timing
Table 4–52 describes the Cyclone FPGA PLL specifications.
Table 4–51. Cyclone Maximum Output Clock Rate for Row Pins
I/O Standard
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
296
285
273
MHz
2.5 V
381
366
349
MHz
1.8 V
286
277
267
MHz
1.5 V
219
208
195
MHz
LVCMOS
367
356
343
MHz
SSTL-3 class I
169
166
162
MHz
SSTL-3 class II
160
151
146
MHz
SSTL-2 class I
160
151
142
MHz
SSTL-2 class II
131
123
115
MHz
3.3-V PCI (1)
66
66
66
MHz
LVDS
320
303
275
MHz
Note to Tables 4–50 through 4–51:
(1)
EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
Table 4–52. Cyclone PLL Specifications (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
fIN
Input frequency (-6 speed
grade)
15.625
464
MHz
Input frequency (-7 speed
grade)
15.625
428
MHz
Input frequency (-8 speed
grade)
15.625
387
MHz
fIN DUTY
Input clock duty cycle
40.00
60
%
tIN JITTER
Input clock period jitter
± 200
ps
fOUT_EXT (external PLL
clock output)
PLL output frequency
(-6 speed grade)
15.625
320
MHz
PLL output frequency
(-7 speed grade)
15.625
320
MHz
PLL output frequency
(-8 speed grade)
15.625
275
MHz


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