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EP1C12F100I8ES Datasheet(PDF) 98 Page - Altera Corporation

Part # EP1C12F100I8ES
Description  Cyclone FPGA Family Data Sheet
Download  104 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100I8ES Datasheet(HTML) 98 Page - Altera Corporation

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4–28
Altera Corporation
Preliminary
January 2007
Cyclone Device Handbook, Volume 1
Tables 4–50 and 4–51 show the maximum output clock rate for column
and row pins in Cyclone devices.
Table 4–49. Cyclone Maximum Input Clock Rate for Row Pins
I/O Standard
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
464
428
387
MHz
2.5 V
392
302
207
MHz
1.8 V
387
311
252
MHz
1.5 V
387
320
243
MHz
LVCMOS
405
374
333
MHz
SSTL-3 class I
405
356
293
MHz
SSTL-3 class II
414
365
302
MHz
SSTL-2 class I
464
428
396
MHz
SSTL-2 class II
473
432
396
MHz
3.3-V PCI (1)
464
428
387
MHz
LVDS
567
549
531
MHz
Note to Tables 4–48 through 4–49:
(1)
EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
Table 4–50. Cyclone Maximum Output Clock Rate for Column Pins
I/O Standard
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
304
304
304
MHz
2.5 V
220
220
220
MHz
1.8 V
213
213
213
MHz
1.5 V
166
166
166
MHz
LVCMOS
304
304
304
MHz
SSTL-3 class I
100
100
100
MHz
SSTL-3 class II
100
100
100
MHz
SSTL-2 class I
134
134
134
MHz
SSTL-2 class II
134
134
134
MHz
LVDS
320
320
275
MHz
Note to Table 4–50:
(1)
EP1C3 devices do not support the PCI I/O standard.


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