EP1C12F100I8ES datasheet(91/104 Pages) ALTERA

Part #	EP1C12F100I8ES

Description	Cyclone FPGA Family Data Sheet

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Manufacturer	ALTERA [Altera Corporation]

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Altera Corporation

4–21

January 2007

Preliminary

Timing Model

External I/O Delay Parameters

External I/O delay timing parameters for I/O standard input and output

adders and programmable input and output delays are specified by

speed grade independent of device density.

Tables 4–40 through 4–45 show the adder delays associated with column

and row I/O pins for all packages. If an I/O standard is selected other

than LVTTL 4 mA with a fast slew rate, add the selected delay to the

external tCO and tSU I/O parameters shown in Tables 4–25 through

4–28.

Table 4–39. EP1C20 Row Pin Global Clock External I/O Timing Parameters

Symbol

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

tINSU

2.417

2.779

3.140

ns

tINH

0.000

ns

tOUTCO

2.000

3.724

2.000

4.282

2.000

4.843

ns

tXZ

3.645

4.191

4.740

ns

tZX

3.645

4.191

4.740

ns

tINSUPLL

1.417

1.629

1.840

ns

tINHPLL

0.000

ns

tOUTCOPL L

0.500

1.667

0.500

1.917

0.500

2.169

ns

tXZPL L

1.588

1.826

2.066

ns

tZXPL L

1.588

1.826

2.066

ns

Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 1 of 2)

I/O Standard

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

LVCMOS

000

ps

3.3-V LVTTL

0

ps

2.5-V LVTTL

27

31

35

ps

1.8-V LVTTL

182

209

236

ps

1.5-V LVTTL

278

319

361

ps

SSTL-3 class I

−250

−288

−325

ps

SSTL-3 class II

−250

−288

−325

ps

SSTL-2 class I

−278

−320

−362

ps

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