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EP1C12F100I8ES Datasheet(PDF) 87 Page - Altera Corporation |
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EP1C12F100I8ES Datasheet(HTML) 87 Page - Altera Corporation |
87 / 104 page ![]() Altera Corporation 4–17 January 2007 Preliminary Timing Model Tables 4–30 through 4–31 show the external timing parameters on column and row pins for EP1C3 devices. tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output register with global clock enhanced PLL with default phase setting CLOAD = 10 pF Notes to Table 4–29: (1) These timing parameters are sample-tested only. (2) These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II software to verify the external timing for any pin. Table 4–29. Cyclone Global Clock External I/O Timing Parameters Notes (1), (2) (Part 2 of 2) Symbol Parameter Conditions Table 4–30. EP1C3 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max tINSU 3.085 3.547 4.009 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 4.073 2.000 4.682 2.000 5.295 ns tINSUPLL 1.795 2.063 2.332 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPL L 0.500 2.306 0.500 2.651 0.500 2.998 ns Table 4–31. EP1C3 Row Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit Min Max Min Max Min Max tINSU 3.157 3.630 4.103 ns tINH 0.000 0.000 0.000 ns tOUTCO 2.000 3.984 2.000 4.580 2.000 5.180 ns tINSUPLL 1.867 2.146 2.426 ns tINHPLL 0.000 0.000 0.000 ns tOUTCOPL L 0.500 2.217 0.500 2.549 0.500 2.883 ns |
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