EP1C12F100I8ES datasheet(85/104 Pages) ALTERA

Part #	EP1C12F100I8ES

Description	Cyclone FPGA Family Data Sheet

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Manufacturer	ALTERA [Altera Corporation]

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Altera Corporation

4–15

January 2007

Preliminary

Timing Model

External Timing Parameters

External timing parameters are specified by device density and speed

grade. Figure 4–2 shows the timing model for bidirectional IOE pin

timing. All registers are within the IOE.

Table 4–27. M4K Block Internal Timing Microparameters

Symbol

-6

-7

-8

Unit

MinMax

tM4KRC

4,379

5,035

5,691

ps

tM4KWC

2,910

3,346

3,783

ps

tM4KWERESU

72

82

93

ps

tM4KWEREH

43

49

55

ps

tM4KBESU

72

82

93

ps

tM4KBEH

43

49

55

ps

tM4KDATAASU

72

82

93

ps

tM4KDATAAH

43

49

55

ps

tM4KADDRASU

72

82

93

ps

tM4KADDRAH

43

49

55

ps

tM4KDATABSU

72

82

93

ps

tM4KDATABH

43

49

55

ps

tM4KADDRBSU

72

82

93

ps

tM4KADDRBH

43

49

55

ps

tM4KDATACO1

621

714

807

ps

tM4KDATACO2

4,351

5,003

5,656

ps

tM4KCLKHL

1,234

1,562

1,818

ps

tM4KCLR

286

328

371

ps

Table 4–28. Routing Delay Internal Timing Microparameters

Symbol

-6

-7

-8

Unit

MinMax

tR4

261

300

339

ps

tC4

338

388

439

ps

tLOCAL

244

281

318

ps

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