EP1C12F100I8ES datasheet(66/104 Pages) ALTERA

Part #	EP1C12F100I8ES

Description	Cyclone FPGA Family Data Sheet

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Manufacturer	ALTERA [Altera Corporation]

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Altera Corporation

Preliminary

January 2007

Cyclone Device Handbook, Volume 1

Figure 3–1 shows the timing requirements for the JTAG signals.

Figure 3–1. Cyclone JTAG Waveforms

Table 3–4 shows the JTAG timing parameters and values for Cyclone

devices.

Table 3–4. Cyclone JTAG Timing Parameters & Values

Symbol

Parameter

Min

Max

Unit

tJCP

TCK clock period

100

ns

tJCH

TCK clock high time

50

ns

tJCL

TCK clock low time

50

ns

tJPSU

JTAG port setup time

20

ns

tJPH

JTAG port hold time

45

ns

tJPCO

JTAG port clock to output

25

ns

tJPZX

JTAG port high impedance to valid output

25

ns

tJPXZ

JTAG port valid output to high impedance

25

ns

tJSSU

Capture register setup time

20

ns

tJSH

Capture register hold time

45

ns

tJSCO

Update register clock to output

35

ns

tJSZX

Update register high impedance to valid output

35

ns

tJSXZ

Update register valid output to high impedance

35

ns

TDO

TCK

tJPZX

t

JPCO

tJPH

t JPXZ

tJCP

tJPSU

t JCL

tJCH

TDI

TMS

Signal

to Be

Captured

Signal

to Be

Driven

t

JSZX

tJSSU

tJSH

t

JSCO

tJSXZ

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