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EP1C12F100C6ES Datasheet(PDF) 40 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 40 Page - Altera Corporation |
40 / 104 page ![]() 2–34 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 Figure 2–26 shows the PLL global clock connections. Figure 2–26. Cyclone PLL Global Clock Connections Notes to Figure 2–26: (1) PLL 1 supports one single-ended or LVDS input via pins CLK0 and CLK1. (2) PLL2 supports one single-ended or LVDS input via pins CLK2 and CLK3. (3) PLL1_OUT and PLL2_OUT support single-ended or LVDS output. If external output is not required, these pins are available as regular user I/O pins. (4) The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the 144-pin TQFP package does not support external clock output from PLL2. Table 2–7 shows the global clock network sources available in Cyclone devices. CLK0 CLK1 (1) PLL1 PLL2 g0 g1 e g0 g1 e PLL1_OUT (3), (4) CLK2 CLK3 (2) PLL2_OUT (3), (4) G0 G2 G1 G3 G4 G6 G5 G7 Table 2–7. Global Clock Network Sources (Part 1 of 2) Source GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 PLL Counter Output PLL1 G0 vv PLL1 G1 vv PLL2 G0 (1) vv PLL2 G1 (1) vv Dedicated Clock Input Pins CLK0 vv CLK1 (2) vv CLK2 vv CLK3 (2) vv |
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