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EP1C12F100C6ES Datasheet(PDF) 36 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 36 Page - Altera Corporation |
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36 / 104 page  2–30 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 The eight global clock lines in the global clock network drive throughout the entire device. The global clock network can provide clocks for all resources within the device ⎯IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin, or DQS signals for DDR SDRAM or FCRAM interfaces. Internal logic can also drive the global clock network for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2–22 shows the various sources that drive the global clock network. Figure 2–22. Global Clock Generation Note (1) Notes to Figure 2–22: (1) The EP1C3 device in the 100-pin TQFP package has five DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and DPCLK7). (2) EP1C3 devices only contain one PLL (PLL 1). (3) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. 8 Global Clock Network PLL1 PLL2 (2) CLK0 CLK1 (3) CLK2 CLK3 (3) DPCLK1 DPCLK0 DPCLK4 DPCLK5 DPCLK2 DPCLK3 DPCLK7 DPCLK6 2 2 From logic array From logic array 4 44 4 Cyclone Device |
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