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EP1C12F100C6ES Datasheet(PDF) 24 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 24 Page - Altera Corporation |
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24 / 104 page  2–18 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 Embedded Memory The Cyclone embedded memory consists of columns of M4K memory blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while EP1C12 and EP1C20 devices have two columns (see Table 1–1 on page 1–2 for total RAM bits per density). Each M4K block can implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. The M4K blocks support the following features: ■ 4,608 RAM bits ■ 250 MHz performance ■ True dual-port memory ■ Simple dual-port memory ■ Single-port memory ■ Byte enable ■ Parity bits ■ Shift register ■ FIFO buffer ■ ROM ■ Mixed clock mode 1 Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Memory Modes The M4K memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. M4K blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 2–12 shows true dual-port memory. Figure 2–12. True Dual-Port Memory Configuration dataA[] addressA[] wrenA clockA clockenA qA[] aclrA dataB[] addressB[] wrenB clockB clockenB qB[] aclrB AB |
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