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EP1C12F100C6ES Datasheet(PDF) 17 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 17 Page - Altera Corporation |
17 / 104 page ![]() Altera Corporation 2–11 January 2007 Preliminary Logic Elements Figure 2–8 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT generates carry- out bits. An LAB-wide carry-in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. Figure 2–8. Carry Select Chain LE4 LE3 LE2 LE1 A1 B1 A2 B2 A3 B3 A4 B4 Sum1 Sum2 Sum3 Sum4 LE10 LE9 LE8 LE7 A7 B7 A8 B8 A9 B9 A10 B10 Sum7 LE6 A6 B6 Sum6 LE5 A5 B5 Sum5 Sum8 Sum9 Sum10 01 01 LAB Carry-In LAB Carry-Out LUT LUT LUT LUT data1 LAB Carry-In data2 Carry-In0 Carry-In1 Carry-Out0 Carry-Out1 Sum |
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