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EP1C12F100C6ES Datasheet(PDF) 100 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 100 Page - Altera Corporation |
100 / 104 page ![]() 4–30 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 fOUT (to global clock) PLL output frequency (-6 speed grade) 15.625 405 MHz PLL output frequency (-7 speed grade) 15.625 320 MHz PLL output frequency (-8 speed grade) 15.625 275 MHz tOUT DUTY Duty cycle for external clock output (when set to 50%) 45.00 55 % tJITTER (1) Period jitter for external clock output ±300 (2) ps tLOCK (3) Time required to lock from end of device configuration 10.00 100 μs fVCO PLL internal VCO operating range 500.00 1,000 MHz - Minimum areset time 10 ns N, G0, G1, E Counter values 1 32 integer Notes to Table 4–52: (1) The tJITTER specification for the PLL[2..1]_OUT pins are dependent on the I/O pins in its VCCIO bank, how many of them are switching outputs, how much they toggle, and whether or not they use programmable current strength or slow slew rate. (2) fOUT ≥ 100 MHz. When the PLL external clock output frequency (fOUT) is smaller than 100 MHz, the jitter specification is 60 mUI. (3) fIN/N must be greater than 200 MHz to ensure correct lock detect circuit operation below –20 C. Otherwise, the PLL operates with the specified parameters under the specified conditions. Table 4–52. Cyclone PLL Specifications (Part 2 of 2) Symbol Parameter Min Max Unit |
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