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EP1C12F100C6ES Datasheet(PDF) 90 Page - Altera Corporation

Part # EP1C12F100C6ES
Description  Cyclone FPGA Family Data Sheet
Download  104 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100C6ES Datasheet(HTML) 90 Page - Altera Corporation

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4–20
Altera Corporation
Preliminary
January 2007
Cyclone Device Handbook, Volume 1
Tables 4–38 through 4–39 show the external timing parameters on column
and row pins for EP1C20 devices.
tINHPLL
0.000
0.000
0.000
ns
tOUTCOPL L
0.500
1.663
0.500
1.913
0.500
2.164
ns
Table 4–37. EP1C12 Row Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.620
3.012
3.404
ns
tINH
0.000
0.000
0.000
ns
tOUTCO
2.000
3.671
2.000
4.221
2.000
4.774
ns
tINSUPLL
1.698
1.951
2.206
ns
tINHPLL
0.000
0.000
0.000
ns
tOUTCOPL L
0.500
1.536
0.500
1.767
0.500
1.998
ns
Table 4–38. EP1C20 Column Pin Global Clock External I/O Timing
Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.417
2.779
3.140
ns
tINH
0.000
0.000
0.000
ns
tOUTCO
2.000
3.724
2.000
4.282
2.000
4.843
ns
tINSUPLL
1.417
1.629
1.840
ns
tINHPLL
0.000
0.000
0.000
ns
tOUTCOPL L
0.500
1.667
0.500
1.917
0.500
2.169
ns
Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing
Parameters (Part 2 of 2)
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max


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