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EP1C12F100C6ES Datasheet(PDF) 84 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 84 Page - Altera Corporation |
84 / 104 page ![]() 4–14 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4–25 through 4–28 show the internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 4–25. LE Internal Timing Microparameters Symbol -6 -7 -8 Unit MinMax MinMax MinMax tSU 29 33 37 ps tH 12 13 15 ps tCO 173 198 224 ps tLUT 454 522 590 ps tCLR 129 148 167 ps tPRE 129 148 167 ps tCLKHL 1,234 1,562 1,818 ps Table 4–26. IOE Internal Timing Microparameters Symbol -6 -7 -8 Unit MinMax MinMax MinMax tSU 348 400 452 ps tH 00 0 ps tCO 511 587 664 ps tPIN2COMBOUT_R 1,130 1,299 1,469 ps tPIN2COMBOUT_C 1,135 1,305 1,475 ps tCOMBIN2PIN_R 2,627 3,021 3,415 ps tCOMBIN2PIN_C 2,615 3,007 3,399 ps tCLR 280 322 364 ps tPRE 280 322 364 ps tCLKHL 1,234 1,562 1,818 ps |
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