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EP1C12F100C6ES Datasheet(PDF) 56 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 56 Page - Altera Corporation |
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56 / 104 page  2–50 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. Table 2–11 shows the possible settings for the I/O standards with drive strength control. Open-Drain Output Cyclone devices provide an optional open-drain (equivalent to an open- collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write- enable signals) that can be asserted by any of several devices. Table 2–11. Programmable Drive Strength Note (1) I/O Standard IOH/IOL Current Strength Setting (mA) LVTTL (3.3 V) 4 8 12 16 24(2) LVCMOS (3.3 V) 2 4 8 12(2) LVTTL (2.5 V) 2 8 12 16(2) LVTTL (1.8 V) 2 8 12(2) LVCMOS (1.5 V) 2 4 8(2) Notes to Table 2–11: (1) SSTL-3 class I and II, SSTL-2 class I and II, and 3.3-V PCI I/O Standards do not support programmable drive strength. (2) This is the default current strength setting in the Quartus II software. |
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