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EP1C12F100C6ES Datasheet(PDF) 55 Page - Altera Corporation |
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EP1C12F100C6ES Datasheet(HTML) 55 Page - Altera Corporation |
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55 / 104 page  Altera Corporation 2–49 January 2007 Preliminary I/O Structure Figure 2–34. DDR SDRAM & FCRAM Interfacing Programmable Drive Strength The output buffer for each Cyclone device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standards have several levels of drive strength that the designer can control. SSTL-3 class I and II, and SSTL-2 class I and II support a minimum setting, the lowest drive strength that guarantees the IOH/IOL VCC GND PLL Phase Shifted -90˚ DQS Adjacent LAB LEs Global Clock Resynchronizing Global Clock Programmable Delay Chain Output LE Register Output LE Registers DQ Input LE Registers Input LE Registers LE Register LE Register Δ t Adjacent LAB LEs OE OE LE Register OE LE Register OE OE LE Register OE LE Register Output LE Registers Output LE Register DataA DataB clk -90˚ clk |
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