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EP1C12F100C6ES Datasheet(PDF) 53 Page - Altera Corporation

Part # EP1C12F100C6ES
Description  Cyclone FPGA Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C12F100C6ES Datasheet(HTML) 53 Page - Altera Corporation

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Altera Corporation
2–47
January 2007
Preliminary
I/O Structure
output pins (
nSTATUS and CONF_DONE) and all the JTAG pins in I/O
bank 3 must operate at 2.5 V because the VCCIO level of SSTL-2 is 2.5 V.
I/O banks 1, 2, 3, and 4 support DQS signals with DQ bus modes of × 8.
For × 8 mode, there are up to eight groups of programmable DQS and DQ
pins, I/O banks 1, 2, 3, and 4 each have two groups in the 324-pin and
400-pin FineLine BGA packages. Each group consists of one DQS pin, a
set of eight DQ pins, and one DM pin (see Figure 2–33). Each DQS pin
drives the set of eight DQ pins within that group.
Figure 2–33. Cyclone Device DQ & DQS Groups in × 8 Mode
Note (1)
Note to Figure 2–33:
(1)
Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin.
Table 2–10 shows the number of DQ pin groups per device.
DQ Pins
DQS Pin
DM Pin
Top, Bottom, Left, or Right I/O Bank
Table 2–10. DQ Pin Groups (Part 1 of 2)
Device
Package
Number of × 8 DQ
Pin Groups
Total DQ Pin
Count
EP1C3
100-pin TQFP (1)
324
144-pin TQFP
4
32
EP1C4
324-pin FineLine BGA
8
64
400-pin FineLine BGA
8
64


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